1. Technical Field
The present invention relates to semiconductor device and method for manufacturing the same, and more particularly, to semiconductor device which comprises a metal gate electrode surrounded by polysilicon layers and a gate insulating film whose edges are thicker than the center portion formed according to a reoxidation process using a thermal process before the formation of an ion implantation region in a process for forming the metal gate electrode using a replacement process to obtain semiconductor device improving its a yield and reliability.
2. Description of the Related Art
In order to achieve high integration and high speed operation of a device, a conventional method for manufacturing a metal-oxide-semiconductor field effect transistor(MOSFET) employs a metal as a gate material instead of polysilicon.
The conventional method for manufacturing the MOSFET includes a replacement gate process for forming a threshold voltage control ion implantation(Vth I/I) region, a gate oxide film and a gate after forming a source/drain region using a dummy gate.
When the replacement gate process is used, a thermal treatment can be sufficiently performed on a substrate to reduce a resistance of the source/drain region. In addition, characteristics of the transistor are improved because a high temperature thermal process after forming the Vth ion implantation region is not performed and the reliability of a gate insulating film is improved because plasma damage due to a gate etching process is prevented.
FIGS. 1a through 1d are cross-sectional diagrams illustrating sequential steps of the conventional method for manufacturing the transistor of the semiconductor device including the replacement gate process.
Referring to FIG. 1a, an element isolating film 12 defining an active region is formed on a p-type semiconductor substrate 11, and a gate insulating film (not shown), a polysilicon layer (not shown), and a photoresist film pattern (not shown) are sequentially formed in the active region.
A selective etching process is performed using the photoresist film pattern as a mask to remove a portion of the polysilicon layer and a portion of the oxide layer, thereby forming a dummy gate 16 which comprises a staked structure of a gate insulating film pattern 13 and a polysilicon layer pattern 15.
A source/drain region 17 is formed by implanting N-type impurity ions using the dummy gate 15 as a mask, and then performing a drive-in process thereon.
Referring to FIG. 1b, an interlayer insulating film 19 is formed over the entire structure including the dummy gate 16, and then planarized according to a chemical mechanical polishing process using the dummy gate 16 as an etch stop film.
Referring to FIG. 1c, an interlayer insulating film pattern 19-1 having a gate groove 20 exposing the semiconductor substrate 11 is formed by sequentially removing the exposed dummy gate 16 and the gate insulating film 13 according to a dry etching process. An ion implantation process and a thermal annealing process can be additionally performed, if necessary.
Referring to FIG. 1d, a gate insulating film 21 is re-formed in the gate groove 20. A metal gate layer (not shown) is formed over the resulting structure including the gate insulating film 21 and the interlayer insulating film pattern 19-1, and then etched according to a CMP process using the interlayer insulating film 19-1 as an etch stop film to form a metal gate electrode 23.
However, in the above-described conventional method for manufacturing the transistor, an overlapped region of the Vth ion implantation region and the source/drain region, exists which results in large junction capacitance and poor reliability for hot carrier.
In addition, the transistor becomes unstable because of the exposed top portion of the metal gate electrode 23 which is easily contaminated during subsequent processes. When a surrounding process for forming an insulating film using SiN is additionally performed in order to solve the foregoing problem, coupling capacitances between layers are increased.